Definitions: Infinite Mass, UCCC and UCTAH

In the old days or with small chips, the system level designer used to request the whole system be created before the design is started.  Back in the day the Analog designer did everything including layout.  Having one guy do everything sounds great but is basically uncompetitive since its serial and non interactive.  (You may believe your own bullshit)   I have met a few fans of the serial approach, they tend to be older than I am defensive, and have low self esteem.  A good chip design program should be able to survive if any member disappears, including the lead.  There may be a delay but the chip goes on. 

I call the "show must go on" approach to integrated circuit (IC) design "Infinite Mass".  This term was coined by a mentor of mine, the late Dave Nack.  Dave used this expression to describe the management style used on him in a bad way.  Dave Nack was my manager at the time and didn't like being told how to manage analog.  He told me that pushing back on good solid analog technique was like "Stopping Jupiter in its path".

Infinite mass is all about project momentum.  This can be an asset or a weapon.  Once you get your team assembled and start the Micro architecture specifications(MAS), you begin to solicit input from the different experts on your team (specific to the task).  Having different people work in parallel in the definition stage builds a relationship between the people and the product.  Micro-management is the enemy here.  Relationships foster dedication and encourage quality.  The Micro-architecture spec completion is a key milestone, even if it has a few blank pages or tables.  It becomes a cornerstone of the chip and its often a living document since things are discovered during the development.  The MAS eventually should contain key details of all the blocks

You can't push back against infinite mass.  At some point after the MAS is defined and the project is underway, each sub-block needs to go through its own architectural phase.  During this time the system is in flux since the analog or digital may not be possible without devastating results.  The team needs to be open to marketing input before the architecture is closed.  However, after the MAS is basically closed, basically the "cooks are in the kitchen" and things need to be stable otherwise they wont finish.  This type of "Infinite Mass" design puts huge pressure on marketing and product definition.  The bigger the chip, the longer marketing has before the architecture is closed.  However, once its closed it should be difficult to change, with "chip death" one of the options.  A late change in the game could take the whole chip from compelling to crap. 

Two killers of SOCs that I know of are:
1.  Unanticipated Collateral Consequence of Change (UCCC): Complex systems can break in subtle ways.  Late in the game a change could "look ok" but cause pathology that may be hard to detect before the chip comes back.  I remind non-analog people that each transistor has at least 4 connections: Drain, Gate, Source,Bulk.  If your design has, say 100,000 transistors, then you have 400,000 connections.  If you change any one, it could affect the others.  The change needs to be carefully executed.  The later you go in the project, the more of the connections are "made", therefore increasing the risk of change while increasing verification.  Its actually more complicated than this simple example, which leads to the second killer

#2.  Underestimation of the complexity of the task at hand: (UCTAH)  This assumes that the thing you don't know about is easy to solve or doesn't matter.  This is big for people who like to assume things or think they know it all.  One hidden killer in optical sensors is the package.  Delivering a reliable part that detects light in reasonably cheap package is very challenging.  You can have the best circuit designer in the world but he won't help make your part survive the re-flow soldering process.  The answer to UCTAH is honest feedback and a good relationships with peers in your field.  When in doubt, get on the phone and ask a few people you trust.  If you find your understanding of the situation lacking, maybe you have UCTAH.  

Is There no such thing as Analog IP? The Analog IP paradox

My favorite part of IC design is working on the architecture.  At the beginning you have the most freedom to make decisions while enduring an period of study.  Its great to be paid to look at the Journal of Solid State Circuits, text books, design reviews and schematic databases.  Sizing up the task and the different directions it could possibly take.  Balancing risk and time-to-market with a handy IP library and a design team ready to go.  Personally I have had good luck with IP.

I have met analog designers who believe there is no such thing as analog IP.  Most every chip I have ever worked on has circuits re-used from a previous one.  Maybe some of the layouts change, but in the hands of a skilled analog designer the schedule reduction is dramatic.  A full understanding of the block and the history of the circuit block is required.  Of course, we don't want to start with a problematic block or known bad architecture.  If you don't believe in IP you probably have a high opinion of yourself.  Or a big "S" on that t-shirt underneath your button-down shirt.  This paragraph is one of the reasons I created this blog.  Designing everything from scratch each time is hardly street-smart, although may appeal to someone new to the game. It's called Not Invented Here (NIH) syndrome. 

I recall meeting K. Nagaraj at ISSCC a 14 or so years ago.  I used a correlated-double-sampled switched-capacitor integrator he published (around 1996) with Paul Ferguson (lead author).  I said hey Nagaraj thanks for the awesome integrator, made my chip much easier and reduced the risk.  "I never built that circuit" was his response.  Amazing, I told him I read the paper and built it right "off the page".  He said that wasn't normal and that most people cannot build these things.  Does K. Nagaraj believe in IP?  Is it not the IP but who can use it?

I can't over emphasize that its important that you understand the block you "borrowed".  This becomes easier with experience, and the more blocks you have seen.  If you don't have experience with it, you probably shouldn't mess with it.  If an "IP" Tzar were to exist, he/she would have experience with several architectures of ADCs, DACs, PLLs and DC DC converters.  Gray hair is on your head.  You may write a blog about how you make your living making and selling analog circuits.

An example of this I saw recently when a block was being taken from one chip and "performance improved".  The chip lead grabbed the piece of IP but didn't fully understand it.  We were just about to close the micro-architecture spec (MAS) when he did figure out the issue.  As a manager I feel I failed him, however truthfully at this point its easy to change.  The architectural phase did its duty, it kept a mistake from even getting near silicon.  This is all part of the chip-making process.  There will be more posts on this topic in this blog later on.

How much is it worth? Does it have asset value?  Well, the answer to that is "no".   I asked a VP/GM about this at my company, he basically said IP for the sake of IP is worthless.  This was from a guy who sold IP even back "in the day".  IP sitting around has no apparent value.  So unless someone gives it a home in a chip making money, its doing nothing but eating up a forgotten chunk of disk space.  What is strange is that in the right hands, it may save a company risk, time and therefore money.  This doesn't sound worthless to me.  Its the IP Paradox.

STOP and THINK don't waste time

We had a case recently where two methods of analysis didn't agree.  This is normally a time to stop and think.  However, "customer pressure" caused us to lurch forward with a wild-guess fix.  Only I blew the whistle, yes I can be a bummer at work.  I get paid way too much to deal with this sort of thing.  When different measurement methods conflict, there is information to be had!  STOP and THINK.

Circuit analysis can be done in a few different ways.  In most normal situations, a bad circuit is bad, no matter how you analyze it.  For example, we have both AC and Transient analysis in a circuit simulator.  The AC analysis uses linearized elements based on the circuit and its operating condition.  This analysis normally is used to determine stability, gain and bandwidth of a circuit.  The transient analysis is easier for non experts to understand.  Its a time-domain simulation of the circuit which is equivalent to having an oscilloscope probe available to monitor every point in time on the circuit.  The way the waveforms "wiggle" is based on the inputs to the system as well as the properties of the circuit such as gain and bandwidth.

If you have a case where the AC analysis says your circuit is really fast and functional, and the transient analysis shows a "flat line" or no response, then you have an issue.  The correct thing to do in this situation is to determine WHY the two analysis conflict.  Fast vs. dead?  Both can't be true.  One analysis says the circuit is fast, the other says it doesnt work. Never in this situation is it worthwhile to "fix" the dead circuit or "force it" to work.  Don't bother until you understand why the two simulations give different results.  Any other activity is a waste of time, unless you hate your job and just want to burn time.  I discussed this with a circuit expert at Maxim today with violent agreement.

 A real-world example of this is op-amp slew.  This is a nonlinear phenomena when a circuit does not have enough current to charge and discharge the junctions in the circuit fast enough.  A linearized "AC" analysis will show health.  However, a transient analysis would show a response in slow motion.  What this means, is that for small signals the circuit is fast, but for larger "wiggle" the circuit is starved for current.  In this case, you conclude you "didn't use enough current" in the main design.  Once you allow the circuit to have the current it requires, the two response should match.  Your circuit was broken.  When a linear analysis does not match a transient analysis, 9/10 times it has to do with something nonlinear in the system.  The rules of superposition no longer apply.  Search for the nonlinearity and you will find your problem. 

In conclusion, when different methods of analysis don't agree, you need to STOP and THINK about why they don't.  That is enough information in itself.  Don't assume a fix for something you don't understand, or you will fix it again.. and again.... and again... and again...

Normal order of Failures watch your DC bias

During our group meeting on Friday we discussed a recent Journal of Solid State circuits paper.

Yunzhi Dong and Kenneth Martin "A High-Speed Fully-Integrated POF Receiver with Large-area Photo Detectors in 65nm CMOS" IEEE JSSC Sept 2012 pp2080.

This is a very well written paper starting from the dynamic behavior of photo diodes to the implementation of the receiver.  The receiver looks similar to those I have worked on in the past and the line-up clever with a fully-differential transimpedance amplifier with a replica diode at the input.  A single point gain control after the TIA followed by filtering and a buffer amplifier to get the signal out.  Dong and Martin chose a continuous time high-frequency boost approach these have advantages in power and jitter tolerance but are more difficult to design.  Thats why its Dong's Ph.D.    I really liked the impedance analysis at the TIA input.  The TIA itself was very clever and amazingly works at 65nm voltage levels.  The eye diagrams look great that tells you something.

Dong did a good job in his design and his layout.  If you built a circuit with the exact same schematics as Dong and Martin and did a different layout, it may not work at all.  At GHz rates the layout is so critical that a missing shield or imbalanced line could ruin, or worse yet, degrade performance.  When debugging a receivers like this in the past I have seen the same issues over and over (at the chip level):
#1  Bad circuit architecture (wrong circuit, incorrect design, incorrect specs. )
#2  Bad Layout (imbalanced, mirror symmetric, IR drops, coupling)
#3  DC Bias (improper DC bias point)

#1 is obvious.  #2, I have met analog designers who claim that the layout is not important.  Maybe they don't respect the job of a good layout designer.  Depending on the SNR and bandwidth requirements your layout sensitivity can go from non-existent to extreme.  #3.  Its amazing how many 15yr+ analog designers mess up DC bias.  Famous quote "That voltage was close to what I needed so I simply used it."  If you hear that quote, get ready for the lab.

Trade Offs vs. Marketing

Sometimes there is a trade-off between being reactionary or doing the right thing.  Its easy to confuse poor product definition with inability to execute quickly.  We have a customer who wants us to create a lower-cost version of a part they are already using.  However, unable to get information on exactly how the part is being used, its impossible to predict how the replacement part will act in their system.

A key challenge in light sensor design is that the chip is sensitive to geometry.  The light sensor is an optical-mechanical-electrical solution.  So, depending on the environment around the part, the behavior will change.  Reflections, shadows, and objects near the sensor can affect its performance.   In general, if the customer is not willing to share information about their system, the odds of giving a satisfactory solution are low.  Its hard to pass up money these days, but sometimes a customer doesn't understand when they are being unreasonable.

I told our marketing team that instead of trying to rush to second-source a part without system specifications, its better to look ahead into the future and anticipate where the customer is going.  This allows a normal design in process.  This is especially true when not all the technology to build the replacement part is ready.  We need to aim to exceed the performance of the present customer solution with a new part that is lower in cost than their present solution.  By saying no to the short-term business, we can create a better more valuable part.  This more valuable part will be useful to many customers, since at least one is already buying an inferior part.

The beginning

Hello!  I have been considering writing a blog related to my life as an anlog integrated circuit designer.  I have been working with analog circuits now for over 35 years.  I have witnessed hundreds of millions of dollars in product developent, not all of it good.  Hence my desire to document.  Maybe a nugget from this blog will help you save time and money.  Or maybe you think chip design and debug interesting.  Stay tuned!