RESETN = !RESET or "not RESET" no.. thats not a typo. Analog guys be careful!!
Reset.. how bad could it be?
A common theme for mixed-signal conversations has to do with the chip RESET function. We all take for granted that when we turn on electronics they always behave the same way. It turns out that many designers spend time behind the seems to insure a consistent experience with their chip.
The way to make a chip behave each time is to have a RESET circuit. A IC's RESET function normally is comprised of several different circuit blocks. These blocks work together to insure that the chip always starts from the same initial state. Some chips have firmware or microcontrollers so they can remember a previous state. This is not what is being discussed here. Before that microcontroller "wakes up" to put the device in a known state, is has to come up in a known safe state to begin with. That is what the RESET is for.
The first part of a RESET system is an element that creates a reset event. This event could be a pin on the chip that needs to be temporarily set to 0V. Other methods look for a rising edge on a power supply, others look for the power-supply to get above a certain level. Hysteresis is important since clearing the RESET state often involves a dramatic increase in current consumption. Without hysteresis the inrush of current can cause a mini brown-out and can even cause oscillations as the circuit comes in and out its reset state. Even more complicated RESET systems look for the presence of a clock (clock detect), holding the device in a safe state until the on-chip clock generator and possibly multiple power supplies come online. In practical implementations I have seen several techniques used in practice. People have their favorites but often this is shaped by the products they design. The toughest resets I have worked with have been those required for cell-phones (the battery removal problem).
The reset generation circuits are a class that must operate with very low supply voltage. The skilled designer needs to make sure the power-on circuit behaves on power up and discharges (how the reset circuit resets itself) on power-off. There are common circuits but in practice some of the hardest to build. The reason being is the design space includes a supply voltage of 0. It is common for circuits like these to include resistors since they still can pull a current when there is not enough voltage to turn on a transistor. Capacitors can also be used to siphon current from the supply ramp, its normally washed out by an external bypass cap the inrush added by this is trick is small. These circuits should be Monte-Carlo'd and have the ability (ideally) to be disabled via an external pad/pin, bond-option, fuse or FIB target on the layout in a high metal layer. I'll do another blog post on RESET disasters. If your reset circuit has more than 30 or so devices you are doing it wrong! Simple is better!
The second important key part of an IC reset subsystem are the circuits that receive the master RESET signal from the above listed set of reset detection circuits or pin. These circuits distribute the RESET and implement the clearing of the memory/previous state. There are two classes of RESET that are employed, asynchronous and synchronous reset. The asynchronous RESET works without the presence of a clock. Normally this is distributed as RESETN (!RESET) and is held high until the chip is allowed to run (low). These can be connected to a resistor and capacitor off-chip and often (but not always) come out of the chip as a pin. The synchronous reset happens on a clock edge, allowing (in theory) several chip systems to come online at the same time or in a known (reliable) sequence. What I didn't learn in school was how tough making a product quality RESET can be.
I will guess most of the people who read this blog have struggled with a RESET issue at least once. Its normally a test setup killer since you can lose control of the state of the chip. Customers get unpredictable results. Chips randomly burn up. Experiments may become non-repeatable since some internal circuits could be affected by a previous experiment. Work-arounds include driving the reset pin off-chip and using a serial port to force every state before the chip is used. The old "hidden state" problem is a big pain.
The good news is that there are experts in RESET. This is where our digital designer friends can make a huge difference. I know analog guys think they are smart but its Street Smart to leverage digital design experts on how the reset works at nearly every level. A good whiteboard discussion. Digital designers are also good at making sure (by design) that their digital circuit does reset properly. I know at least one other guy who has written a script to check a digital design (from analog person shhhh) for flip-flops without a reset (and found them!). A flip-flop is not just a flip-flop. Think about it before putting on the schematic. What happens if its not reset? Sometimes its ok and other times its not.
The digital verification tools can check the reset function for hidden issues such a sequencing with proper modeling. The digital designer can't even launch a simulation run until the basic initial (RESET) state is set. Also some resets must take longer than others or may depend on other things happening in the chip. An example of this is power-gating where parts of a chip are shut down to save battery life. When the power islands go up and down the digital needs to act predictably. The new power island techniques add yet another level of complication.
When it comes down to it, the start-up state and how to get out of it should be a priority early on in your design program. Make sure you have (ideally) proven reset IP and thank the designer who provided it. If you need to design your RESET circuit, make sure a gray-beard with related experience is available. Finally the RESET sub-system should be designed, simulated and verified by a qualified event-based style (DIGITAL) design expert. Reset is not something you simply "psych out" unless your chip is supposed to smoke.
