Street Smart Analog Terminology

In everyday life I basically use these terms over and over again.  I assume that everyone knows what these things mean, but that is probably not the case. So I am going to publish and maintain a list of my "Streetsmart Analog Lingo".

Most of this lingo comes from other smart people in this business.  I can't give credit to everyone.  The late Dan Ray was an expert in this area.  Dan was a founder at Level One and one of my first mentors.  He was awesome in analog.  Tim Dyer (my identical twin brother), Perry Heedley (CSUS), David Viera, Patrick Isakanian, Paul Hurst, Stephen Lewis, Bob Pease, and Dave Nack contributed some of these over the years. 

Street-smart Analog Lingo:

A1 Release:  Release of silicon on the very first version.  This happens very rarely, maybe 1% of the time with analog circuits.  Assuming it will happen is unrealistic and can actually be discouraging.

All Layer:  A design that requires all mask layers to be changed or all new masks

APR:  Automatic place-and-route.  Machine generated layout.  Also called DDA (Digital Design Automation)

Antenna:  Long piece of metal touching gate-poly - can damage poly leading to huge offsets. Also can be a single-ended wire (test-point) on a circuit board operating at over 200 MHz.

Bake It:  Temperature cycle

Boomerang:  Bad evaluation board returned from the customer

Brown-thumb:  A designer who uses "unconventional" techniques or "special tricks" to do design.  Often these characters are associated with unreliable circuit designs and poor execution.  Also associated with using poor methodology and bad practice.

Change layer:  Metal layer dedicated for changes/programmability

Carpet Bomb It:  see NFS

Chip Designer:  There are only chip designers.  All block designers should be interested in how their circuit affects the chip then are working on.  Especially important in a (System on a Chip) SOC

Cup-cake:  Cross sectional shape of copper metalization

Expert-layout schematic: an analog schematic without any layout hints or notes

E^Overnight:  Bit-error rate test requiring no errors if left overnight. 

Fib Slut:  A part that has been in and out of a "Focused Ion Beam" (FIB) more than twice

Follow the Dollar:  The process of following the customer's money to your paycheck.  It should be easy to "follow the Dollar" unless you know you are operating at a loss.

FOS Schedule: Full of shXt schedule.  Normally used to get management pregnant on a chip design program

50% Schedule: Project schedule that requires everything to go perfectly.  No competent marketing person or design manager ever commits to a 50% schedule unless its a FOS Schedule.

Hair-dryer:  Heat gun

Hare:  high-power low-impedance approach to design. Opposite of tortoise.

Hidden state:  Circuit state not designed - normally from a bad reset circuit. Often appears when an over-confident analog person does digital design. 

Leapfrog test-path:  Analog test-path that allows blocks in a analog signal chain to by bypassed for debug.

Luck:  When the mistakes you made didn't matter

Irregular layout:  Any circuit block that is not square or rectangular. Also called "donut block" or "block with a tit on it"-Dan Ray. 

Magic-fingers:  The opposite of brown-thumb.  Someone who executes

Magic-circuit:  Circuit designed by someone who doesn't understand it.  Often a Brown-thumb.

Magic smoke:  When it leaves the chip it no longer works.

Maskview: Job-deck view which is a manual mask check.  Ideally a "Zen" moment and never to be done in a panic.

Metal-up; Metal:  A design that requires just metal changes - quicker and bypasses HTOL.  Often a way to patch a design for a quick fab turn.

MAS Document  Micro-architecture spec document or "chip Bible".  So useful but so shunned, a one stop shop for circuit-block and interface information.

Nack Hack:  {names after the late Dave Nack}  A circuit board without a "toe-tag" containing unknown changes or hacks.  

Nail:  Type of die probe that is simply a piece of metal

Noisy Neighbor:  Noisy circuit block interacting with nearby circuits 

NFS:  Nuke it From Space {Aliens II}.  A circuit that is flakey or has unknown issues that should be completely re-designed.  A circuit or a layout that is fundamentally flawed.

Onion Peel:  (peel the onion) When a chip revision comes back and a new problem is uncovered (often hidden by what was fixed)

Pencil Tap:  Before GPIB and Labview we would tap knobs with pencils for fine-tuning

Pizza Mask: A multi-reticle run of silicon.  Can be "metal-up" or all-layer.  Normally used for debug or system level designs without a full set of models.

Poke it with a stick: Low risk vehicle in trying a new technique or new process.  Also used in debug to determine if the problem is sensitive to external stimulus.

Popcorn: moisture in the package causing trouble in re-flow splitting the part

 Put a fork in it: Basically done, any more effort spent on it is wasted

Leakage:  sub-threshold drain-source current in MOS that makes a sensitive temperature sensor. 

Relentless beating:  To solve a problem with several simultaneous solutions

Sim Slave: Design resource asked to do simulations without understanding

Smoke Test:  First power-up of new silicon

Spoiled-via:  Connection between metals that is open or flakey

Tape-out:  Sending the plans of the chip to the FAB for mask generation.  An important milestone for non-experts but meaningless for true experts, since you may have a "Turd"

Team Analog:  Design, debug or architecture work done in an interactive manner. 

Testbus:  Test path snaked through an analog design that goes to an external pin for debugging

Trainwreck:  When two layouts crash-into eachother.  Also a machine-generated schematic or one in which the wires cross.

Thump test:  Finding a signal integrity problem (loose connection) by thumping your fist on the bench. 

Turd:  An incompletely verified piece of silicon. Due to time-constraints, not all simulations are run.

Works by accident:  Analog circuit or subsystem category with a flaw that works fine anyway. For example critical layout sensitivity that happens to balance, when later edited may surprise fail. 

Works in simulations:  Analog always works in sims... famous last words.

You can't bullshit electrons:  Just because you designed it doesn't mean it will work

Zap:  ESD testing

Zorch:  Catastrophic failure of a DC DC converter IC. (Parasitic Zener)