Missing Teeth

With switched-capacitor circuits, one of the most critical parts of the design is the clock generator.  As a friend of mine once said:

"When your switched-capacitor circuit doesn't work, check your clocks.  After that, check your clocks again."   (Perry Heedley-1998)

It was back in 1999 we had our first-generation gigabit SOC back in the lab.  The process was 0.35u.  Supply 3.3V.  We had a strange problem with non-uniform sampling.  When we sent the clock out the "test-bus" we saw that it had missing pulses.  Missing pulses are not a good thing and the Flash ADC ENOB was terrible.  Lots of tones!  On the scope the clock looked like a boxer who was missing teeth.  We also had supply dependence where high supply and cold spray made it worse.  What was going on?

On Friday I met a new friend who had a similar story.  (So sorry buddy!)  This inspired me to write this blog post on this common screw-up.  If I have seen one common mess-up in that the something goes wrong with a reference clock.

In these larger Ethernet chips, we distribute the clock as a differential signal.  The advantage of going differential is that the signal is not affected by clock skew and the rise/fall time match perfectly (by design).   If you distribute critical clocks with single-ended circuits stop reading now since you are hopeless.  The differential approach gives you a uniform sensitivity to noise on the chip and in the environment (see Ali Hajimiri's wonderfully written "Low-Noise Oscillators").  Another advantage of using a differential clock, is that ideally you can send it across power-supply domains. (when things are normal)

Now if you want a good non-overlapping clock its easy to go overboard.  Normally you have a "non-overlapping clock generator".   Its a circuit who's job it is to make sure a set of clocks do not occur at the same time.  A trade-off in those designs is the rise/fall time.  If the clock coming out of the block has a fast rise and fall time, the clocks are less apt to overlap.  However, this comes at a cost.  The designer keeps increasing the size of the generator to make the output edges faster and faster.  Eventually coming to a solution.  There is a trade off between non-overlap time and Operational Transconductance Amplifier (OTA) settling. It almost always seems easier to use a big clock buffer transistors than to beef-up your amplifier bandwidth.

A huge pitfall of these "massive" clock generators is that they can generate huge amounts of noise and "ground bounce".   Or as Stephen Lewis (UC Davis) would say "Making sparks".  The huge clock buffer circuits create massive amounts if dI/dT.  Huge current spikes with peaks upwards of close to an amp can find there way into your big clock buffer.  These currents hit your package (with inductance) which translate them into huge voltage spikes.

When it comes to "noisy neighbors" on a chip, it always takes an aggressor and a receptor.  In this case, I was able to debug this animal but putting the clock-generator into a schematic along with a simple package model consisting of package inductance.  I then put the clock source on a different power-supply in my schematic to see what happened.  I did this by hand in HSPICE since I am not the hugest fan of schematic capture.  I did this hand-written test-bench in real time in the lab right next to an oscilloscope with the bad clock on it.  It was me, Sailesh Rao, Jim Parker and Dave Nack all gathered around the setup.   I kept tweaking the test-bench, and Q factor (4) on the bondwires until BINGO.  I was able to match the waveform from the scope in HSPICE.  High-five from Dr. Rao!  What happened?

The ground-bounce was so big that it was measured in VOLTS.  Yes, our 3.3V supply had volts of ground-bounce on it from a huge clock generator.  By increasing the temperature or lowering the supply on the clock generator, we could work around the problem.  This part wasn't going to sample in this state.  The ground-bounce was too big from uber-big clockgen!

The main PLL and the ADC with the uber-clockgen were on different power supply pins.  Analog guys like to use A BUNCH of power supplies, normally to keep noise from coupling around.  However, this can sometimes backfire.  When breaking up power-supplies its important to visualize the return paths of all the currents and how they will affect each-other.  In this case, the PLL sent the clock to the ADC who caused so-much ground-bounce that the buffer amplifier receiving the clock in the ADC missed pulses.  This happened since the amplifier only had a common-mode range of about a volt, with more than a volt of ground bounce between the supplies.

So now, hopefully everyone knows that you can make a clock-generator "too-big".  A technique to finding these is to just turn-on base-layers in your layout and look for huge MOSfets.  Always ask yourself why you have a big transistor, since everything in the area will know about it.  Also people should be aware that more supplies are not always better.

So what is a solution?
A.  NERF your clockgen - Simulate it with bondwires
B.  Add on-chip bypass capacitors to prevent dI/dT from hitting the bondwire
C.  Improve the common-mode range of your clock buffer.
D. Design a set of  inter-supply "repeaters" with huge common-mode range
E.  Use DC Blocking capacitors

We solved this one with A and B.  The ADC worked much better after we fixed that.  We still had more challenges but....

"When your switched-capacitor circuit doesn't work, check your clocks.  After that, check your clocks again."