LC sTank

Recently I have taken on a new project that has LC tank based PLLs on it.  The company I now work for has a long history with this type of block, and I appreciate that.  I have seen a few bad LC tank PLLs in my time.  They can fail in several different ways.  The most interesting failures with oscillators is that when they don't.

I have seen ring-oscillator, relaxation-oscillator and LC tank based oscillators used as the time-base for a system on a chip (SOC).  The type of oscillator basically comes down to its performance and cost.  If you want the best high-frequency reference, the LC tank with its huge die area overhead is hard to beat.  The LC tank has a natural filtering property to it that gives it good phase-noise  filtering, leading to lower jitter.   I have mentioned it before but Hajimiri has a great book "Low Phase Noise Oscillators" which is an excellent read.  Hajimiri explains the phase noise filtering and Leeson's equation.

The first chapter of Ali Hajimiri's book is about the "one-port" oscillator.  I found it entertaining that an oscillator only has "one port" in terms of energy.  In electronic design, a port is a way of electrically interacting with it.  A terminal or lead on a chip is an example of a port.  Ali explains that an oscillator on a chip will go forever if there were no "real losses".  Real losses are where the "power goes".  So Ali states, if you add back enough power to a "one-port" oscillator to compensate for its internal "real" losses, then it will oscillate forever. Ali's observation is insightful.

It was around the 2005 time-frame and we had a 90nm test-chip back in the lab with a 3.2GHz LC tank oscillator based PLL on it.  The input reference clock was 50MHz or 100MHz and the goal was 1ps RMS jitter measured in band.  The clock came back and looked great, phase noise looked "weird", but the jitter was excellent.  The phase-noise had a distinct lack of bandwidth, the loop bandwidth was lower than expected.  So what was wrong with this one?

We were characterizing the jitter over temperature and noticed something.  At temperatures above 120F, the LC tank would stop oscillating.  The output signal would fade out.  Sometimes you could get it to start by "jacking up" the tank current.  On this tank we pushed a adjustable current into a "center-tap" of the dual inductor at the point of symmetry at the center of the tank.   The adjustable DC current supplies N-MOSFETS connected in positive feedback that created the regeneration.   If we made the current high enough it would oscillate at a higher temperature, but still would die at a slightly higher temperature.  Supply voltage was a "weak knob".  The oscillator worked great at cold temperature.

Schematic level simulations didn't show any problems with the design over temperature.  Even with package models.  No problems observed in any corner with interface blocks.  Since we were closing in on the oscillator, the next step after that is the "extracted" simulation set.  These simulations can take a very long time to run.  So. to save time. we broke the PLL layout into "sections".  We then swapped in an RC netlist for the "section" of the PLL under study for temperature sensitivity.  We rotated through the block and eliminated all the high current blocks (amazingly).  Main inductor, power-grid on the main current source, high-frequency divider and the output buffer were all fine layout wise.

So now this is where Hajimiri ties in.  The "last" place we looked was the varactor circuit.  This was a tricky animal that combined a varactor with a trim-cap array.  A trim-cap array is normally used at start-up for an LC tank based PLL to center itself.  At start-up the correct number of unit capacitors are selected before the PLL loop is allowed to lock.  This "Loop Filter" block is interesting in that it has a "lot of plumbing", and that was the problem.  When putting in an RC extraction of the Loop Filter, we identified the bad layout.

It was series resistance to the capacitor "C" in the "LC" tank!  A pair of long skinny wires connected the inductor to the Cap.  It was the first time I saw a parasitic resistor stop a circuit in its tracks.  The resistances in the routing increase with temperature.  The real-loss in this poorly routed line was enough to upset the operation of the LC tank.  The wire on the chip would heat up and the circuit would stop oscillating.  What was interesting, is that the simulation and the lab failed within 10 degrees of each other.  It was an amazing correlation.  The new simulations also showed the change in phase-noise response, which was the first symptom of the badness. Of course after we identified this the layout fix was easy.

So, in the LC tank PLL, don't spend so much time on L that you forget about C.  Real loss is the enemy.